Very Linear Ramp-Generators for High Resolution ADC BIST and Calibration
نویسندگان
چکیده
Two very linear ramp-generator designs are presented. The circuits are to be used in high-resolution ADC built-in-self-test (BIST) and on-chip calibration. The first design is to charge a capacitor by a small current, which is linear enough to test 14-bit ADCs. The second design is in a relaxation oscillator architecture. It is linear enough to test up to 12-bit ADCs. The two designs have been fabricated in CMOS 2um and 1.2um processes separately.
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تاریخ انتشار 2008